Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory used in modern electronics, one common type is RAM (random-access memory). RAM is characteristically found in use as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to ROM, which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. Memory devices that do not lose the data content of their memory cells when power is removed are generally referred to as non-volatile memories. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates.
Yet another type of non-volatile memory is a Flash memory. A typical Flash memory comprises a memory array, which includes a large number of memory cells. Each of the memory cells includes a floating gate embedded in a field effect transistor (FET). The cells are usually grouped into sections called “erase blocks.” Each of the cells within an erase block can be electrically programmed selectively by tunneling charges to the floating gate. The negative charge is typically removed from the floating gate by a block erase operation, wherein all floating gate memory cells in the erase block are erased in a single operation.
Two common types of Flash memory array architectures are the “NAND” and “NOR” architectures, so called for the resemblance which the basic memory cell configuration of each architecture has to a basic NAND or NOR gate circuit, respectively. In the NOR array architecture, the floating gate memory cells of the memory array are arranged in a matrix. The gates of each floating gate memory cell of the array matrix are connected by rows to word select lines (word lines) and their drains are connected to column bit lines. The source of each floating gate memory cell is typically connected to a common source line. The NOR architecture floating gate memory array is accessed by a row decoder activating a row of floating gate memory cells by selecting the word line connected to their gates. The row of selected memory cells then place their stored data values on the column bit lines by flowing a differing current if in a programmed state or not programmed state from the connected source line to the connected column bit lines.
A NAND array architecture also arranges its array of floating gate memory cells in a matrix such that the gates of each floating gate memory cell of the array are connected by rows to word lines. However each memory cell is not directly connected to a source line and a column bit line. Instead, the memory cells of the array are arranged together in strings, typically of 8, 16, or more each, where the memory cells in the string are connected together in series, source to drain, between a common source line and a column bit line. The NAND architecture floating gate memory array is then accessed by a row decoder activating a row of floating gate memory cells by selecting the word select line connected to their gates. In addition, the word lines connected to the gates of the unselected memory cells of each string are also driven. However, the unselected memory cells of each string are typically driven by a higher gate voltage so as to operate them as pass transistors and allowing them to pass current in a manner that is unrestricted by their stored data values. Current then flows from the column bit line to the source line through each floating gate memory cell of the series connected string, restricted only by the memory cells of each string that are selected to be read. The stored data values of the row of selected memory cells are thereby placed on the column bit lines to be sensed.
A problem with programming Flash memories is that programming and/or erasure typically involves applying a high voltage to elements of the memory array. As memory device features are scaled smaller in modern integrated circuit processes the use of high programming and erasure voltages becomes a more of an issue due to increased electric fields and coupling across smaller features and thinner oxides. This can require the usage of larger feature circuit elements or differing circuit designs in these portions of the memory array in order for them to be able to withstand the higher programming voltages.
Additionally, the high programming voltages applied to the individual floating gate memory cells can lead to problems with write fatigue of the selected memory cells and an increased likelihood of disturb problems in the unselected memory cells of the array. The reduced feature sizes also may lead to increased resistances in the memory device elements and, in particular, in the floating gate memory cells, reducing the overall performance of the memory device, reducing the practical limits of memory string length in cells, reducing memory string current, and increasing the applied voltage levels as they are raised to compensate.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for improved Flash memory arrays.